Electrical Engineering and Computer Science, University of Michigan
Sparse Coding ASIC Chips for Feature Extraction and Classification
Wednesday 04th of May 2016 at 12:00pm
Hardware-based computer vision accelerators will be an essential part of future mobile and autonomous devices to meet the low power and real-time processing requirement. To realize a high energy efficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to the underlying algorithms, which is an advantage over software-based solutions and general-purpose hardware. In this talk, I will present three application-specific integrated circuit (ASIC) chips that implement the sparse and independent local network (SAILnet) algorithm and the locally competitive algorithm (LCA) for feature extraction and classification. Two of the chips were designed using an array of leaky integrate-and-fire neurons. Sparse activations of the neurons make possible an efficient grid-ring architecture to deliver an image processing throughput of 1 G pixel/s using only 200 mW. The third chip was designed using a convolution approach. Sparsity is again an important factor that enabled the use of sparse convolvers to achieve an effective performance of 900 G operations/s using less than 150 mW.
Join Email List
You can subscribe to our weekly seminar email list by sending an email to
email@example.com that contains the words
subscribe redwood in the body of the message.
(Note: The subject line can be arbitrary and will be ignored)